In the micro-technology field, when it is a matter of producing electronic components, optical or opto-electronic components, or even micro-mechanical components (for example micro-accelerators), silicon substrates are often used, but it must be clearly understood that other materials may also be used, often other semiconductor materials, formed from elements of group IV of the periodic table of the elements (germanium, in particular, and its alloys with silicon), and even groups III-V (in particular GaAs or InP), or even groups II-VI of that table, even LiNbO3, SiC, diamond, etc.
The use, and more particularly the formation, of such hybrid substrates, whether the mixed layer is buried or at the surface, is of particular interest for diverse applications, especially in MOS type devices.
Given the limitations encountered by MOSFET devices in terms of performance, the change of the crystalline orientation of the surface of the substrate used (mostly Si), in the same way as the change of the direction of the conduction channel of the transistors, appears as a simple and effective solution. More particularly, many studies have demonstrated the impact of the orientation of the free surface and the direction of the conduction channel on the respective mobility of holes and electrons. Thus improving the mobility of the carriers (holes) can be obtained via the use of a free surface of orientation <110> in comparison with a usual free surface of type <100>, as recently reported by Yang et al. (“High Performance CMOS Fabricated on Hybrid Substrate With Different Crystal Orientations” by Yang, Ieong, Shi, Chan, Chan, Chou, Gusev, Jenkins, Boyd, Ninomiya, Pendleton, Surpris, Heenan, Ott, Guarini, D'Emic, Cobb, Mooney, To, Rovedo, Benedict, Mo, Ng, which appeared in IEDM 03-2003 pp 453-456). However, the CMOS technologies are based on the simultaneous use of n-MOS type transistors (conduction by electrons) and p-MOS type transistors (conduction by holes). Furthermore, a change of the orientation of the surface has antagonistic effects on the electrons and on the holes, thus necessitating two free surface orientations, which are different for these two types of carrier. Thus it is desirable to be able to produce and to make cohabit two types of orientation on the same substrate.
Techniques are already known for producing hybrid structures.
Reference may for example be made to WO-2004/059711 or its U.S. equivalent US 2006/0166461, which provide for the formation of a mixed or hybrid structure by molecular bonding of two substrates one of which comprises on its surface two types of zones which differ in their constituent materials; in that document, these two types of zones are obtained by techniques of lithography, etching, thermal oxidation at the surface and polishing so that thermal oxide is left only in etched areas. An improvement on this technique is proposed in the European patent publication EP-1 923 912 or its U.S. equivalent US 2008/0079123, which teaches the formation of a sacrificial layer ensuring the flatness of the surfaces finally exposed.
Furthermore, the aforementioned document of Yang et al, proposes, instead of using thermal oxidation to fill the etched zones, to hollow out cavities by etching in an SOI substrate (thus with a semiconductor layer above a buried electrically insulating layer), through the insulating layer, and to cause these cavities to be filled by epitaxy from the bottom of those etched zones, which bottom is constituted by a material (under that insulating layer) chosen to have different crystal properties to that of the unetched zones. This technique is commented upon in more detail in “Hybrid-Orientation Technology (HOT): Opportunities and Challenges” by Yang, Chan, Chan, Shi, Fried, Stathis, Chou, Gusev, Ott, Burns, Fischetti, Ieong which appeared in IEEE Transaction on Electron Devices, Vol. 53, No 5, May 2006, pp 965-978. It should be noted that this technique is incompatible with the desire to have a buried electrically insulating layer that is continuous, since it requires the use of an oxide layer which must be pierced at intervals, opposite each of the etched zones, to enable the growth of zones by epitaxy.
Another production technique is described by Yin et al. (see “Direct Silicon Bonded (DSB) Substrate Solid Phase Epitaxy (SPE) Integration Scheme Study for High Performance Bulk CMOS” by Yin, Sung, Ng, Saenger, Chan, Crowder, Zhang, Li, Ott, Pfeiffer, Bendernagel, Ko, Ren, Chen, Wang, Liu, Cheng, Mesfin, Kelly, Ku, Luo, Rovedo, Fogel, Sadana, Khare, Shahidi, which appeared in 1-4244-0439-8/06/$20.00 © 2006 IEEE,); this technique is based on using a DSB (Direct Silicon Bonding) structure, that is to say one obtained by direct bonding of two silicon substrates with different crystal orientations: by lithography and ion implantation, zones of one of the substrates are selectively rendered amorphous through its full thickness to reach the interface between the two substrates, and the zones rendered amorphous are induced to recrystallize following the crystal properties of the other substrate; it is stated that unless, before recrystallization, trenches are formed between the zones rendered amorphous and the zones that have not been rendered amorphous, two competing recrystallization phenomena are observed, starting from the underlying substrate (following a first crystallographic orientation) and starting from adjacent zones (following another crystal orientation). It should be noted that this technology is incompatible with the presence of a buried electrically insulating layer along zones of different crystallographic orientation (that zone would prevent the crystallization following the crystallographic orientation of the underlying substrate.
Yang et al. (see “Silicon-on-Isolator MOSFETs with Hybrid Crystal Orientations” by Yang, Chan, Kumar, Lo, Sleight, Chang, Rao, Bedell, Ray, Ott, Patel, D'Emic, Rubino, Zhang, Shi, Steen, Sikorski, Newbury, Meyer, To Kozlowski, Graham, Maurer, Medd, Canaperi, Deligianni, Tornello, Gibson, Dalton, Ieong, Shabidi which appeared in Symposium on VLSI Technology Digest of Technical Papers, 2006.) have demonstrated, via a simulation, the importance of depositing such a continuous buried electrical insulator under the zones of different orientation, and have proposed a modification to their method of production (as defined in “Hybrid-Orientation Technology (HOT): Opportunities and Challenges” by Yang, Chan, Chan, Shi, Fried, Stathis, Chou, Gusev, Ott, Burns, Fischetti, Ieong which appeared in IEEE Transaction on Electron Devices, Vol. 53, No 5, May 2006, pp 965-978) aimed at minimizing the interruptions of the buried electrically insulating layer; this modification consists in providing for the etching through the buried electrically insulating layer to be made over a section less than that of the cavity hollowed out in the layer situated above that insulating layer. It can nevertheless be understood that this improved technique is still incompatible with the desire to have a buried electrically insulating layer that is continuous.
There is thus the need to be able to produce hybrid substrates comprising, adjacent to a buried electrically insulating layer, a mixed layer formed from zones having predefined crystallographic orientations (two different orientations, in practice, but it is understood that it may, in certain cases, be useful to be able to make such a layer comprise zones having, in a predefined manner, one of three (or more) different orientations.